The JRA ULISINT covers three fields of large-area tracking and vertex detectors, each of them backbones of the upcoming CBM and PANDA detectors at FAIR:

Technologies and procedures towards the integration of the three types of detectors into full systems will be explored.

 Description of work and role of partners

Task 1 (GSI)
Integration of a low-mass large-area silicon micro-strip detector system for particle tracking: development of a high-density front-end electronics board for the readout of an ultra-light large-area silicon micro-strip tracking system; exploration of technologies for their mass-production; definition of procedures and tools for their assembly into tracking detector modules; definition of procedures for the module integration into the mainframe/thermal enclosure of the CBM micro-strip tracking system.
1.1 - Provision of ultra-light Aluminum-Kapton micro-strip readout cables for bonding tests on various FEB substrates. (GSI, SE SRTIIE)
1.2 - Design and production of high-density input patterns on various FEB substrates. (GSI)
1.3 - Investigation of thermal, mechanical and electrical quality of the substrates, metal structuring quality, and TAB-bonding of cables to the substrates. Definition of the FEB basis material. (GSI, SE SRTIIE)
1.4 - Development and production of a demonstrator FEB with several CBM-specific prototype readout chips.
1.5 - Development and production of a demonstrator FEB with full integration of readout chips and services for power supply, data links and controls. (GSI)
1.6 - Development and production of the demonstrator of a fully integrated FEB, including high-density input stage. (GSI)
1.7 - Evaluation of the FEBs on test stands; TAB-bonding of sensor-cable assemblies to FEB demonstrators.
1.8 - Definition of procedures for the mass-production of FEBs; definition of procedures and tools for the assembly of multi-sector micro-strip detector modules; solutions, procedures and tools for their integration into the mainframe of the CBM micro-strip tracking detector system, with focus on efficient cooling of the readout section, thermal insulation of readout and sensing sections while enabling feed-throughs of signal cables and reworkability. (GSI, SE SRTIIE, KINR)

Task 2 (INFN-TO)
Integration of a low-mass silicon pixel detector system for particle tracking: a key towards the minimization of material budget in hybrid pixel systems is the reduction of external components and service chips that present-day front end for pixel detectors need for a correct operation. On chip cap-less regulators that avoid external filtering capacitors are employed in chips for mobile phones and other commercial System on Chips, but their use in particle detectors front-end, where the specifications on noise and radiation hardness are particularly demanding, remain to be assessed. Low-power transmitter coupled to ultra-light aluminum based cables allowing high speed electrical transmission over moderate distances (a few meters) would also be useful to avoid extra electro-optical components in zones where the material budget must be minimized. The design of such components and their integration on a realistic front-end demonstrator is therefore the natural complement to the low-power front-end cells with increased functionality developed in the ULISI project. Based on this chip, a full low-mass module prototype will be developed in ULISINT proposal.
2.1 - Development of low-power radiation-tolerant power regulators and data transmitters to be embedded on pixel front-end ASIC. (INFN-TO)
2.2 - Development of low-mass, fine pitch Al cables for off-chip electrical transmission. (INFN-TO)
2.3 - Design and test of a full front-end ASIC incorpo¬rating the circuits developed in 2.1. (INFN-TO)
2.4 - Design of a low-mass front-end module based on the ASIC and cables developed in 2.2, 2.3. (INFN-TO)

Task 3 (GUF)
Integration of a flexible, silicon embedded sensor assembly into a prototype pixel ladder for micro-vertex detection: placement of the active part of the detector onto a support structure with high precision, achieving excellent heat evacuation and sufficient rigidity; exploration of alternative approach as fall back solution if the new technology will not be available in time. Evaluation of technologies allowing reducing the inactive area between individual sensor chips.
3.1 - Evaluation of the mechanical and electrical properties of a prototype silicon embedded chip assembly. (GUF, IMEC)
3.2 - Test series to study the suitability for operation in vacuum and under cryogenic operation. (GUF)
3.3 - Preparation of CVD diamond or TPC/RVC compound support structures. (GUF)
3.4 - Design of the prototype chip assembly. Placement of the sensor chip and design of the electrical interconnection lines. (GUF, IMEC)
3.5 - Integration of the prototype assembly into the detector ladder. (GUF, IMEC)